In the field of a semiconductor device, there have been used planar field effect transistors (hereinafter, referred to as a “planar MOSFET”). Such a planar MOSFET ensures a substantial channel length by controlling a distance between source/drain regions, allowing a gate side wall to be formed in the side of a gate electrode.
FIGS. 1(a) to (c) show a process for forming a gate side wall in a planar MOSFET. FIG. 1 shows a cross section parallel to a channel length direction of a planar MOSFET and perpendicular to a substrate plane. In this process, first, an insulating film 11 and a gate electrode 12 are formed on a semiconductor substrate, and then an insulating film 13 for a gate side wall is laminated over the whole surface (FIG. 1(a)). Next, it is etched back for removing the insulating film layer other than that in the side face of the gate electrode 12 to form a gate side wall 14. Then, using the gate electrode 12 and the gate side wall 14 as a mask, a dopant is ion-implanted (FIG. 1(b)) to form a source/drain region 15 (FIG. 1(c)). In this planar MOSFET, the gate side wall can act as a spacer to ensure a constant distance between source/drain regions and thus to ensure a substantial channel length.
Recently, there has been suggested a field effect transistor (hereinafter, referred to as a “FinFET”) comprising a protruding semiconductor layer projecting upward from a substrate plane, where a main channel region is formed in a plane substantially perpendicular to the substrate plane of the protruding semiconductor layer (side surface), for preventing short channel effect associated with size reduction. Japanese Patent Laid-open Publication No. 64-8670 has disclosed a FinFET where a part of a protruding semiconductor layer makes up a part of silicon wafer substrate and a FinFET where a part of a protruding semiconductor layer makes up a part of monocrystalline silicon layer in an SOI substrate. The former and the latter structures will be described with reference to FIGS. 2(a) and 2(b), respectively.
In the configuration in FIG. 2(a), a part of a silicon wafer substrate 101 makes up a semiconductor layer 103, and a gate electrode 105 extends to both sides over the top of the semiconductor layer 103. In this semiconductor layer 103, a channel region is formed under an insulating film 104. A width of the channel region corresponds to a 2-fold of a height h of the protrusion 103, while a gate length corresponds to a width L of the gate electrode 105. The gate electrode 105 is formed on an insulating film 102 formed in a trench such that it strides over the semiconductor layer 103.
In the configuration in FIG. 2(b), silicon wafer substrate 111, an SOI substrate comprising an insulating film 112 and a silicon monocrystalline layer is prepared, and its silicon monocrystalline layer is patterned to form a semiconductor layer 113, and a gate electrode 115 is formed on the exposed insulating layer 112 such that it strides over the semiconductor layer 113. In the semiconductor layer 113, a source region and drain region is formed on both sides of the gate electrode, and a channel region are formed under an insulating film 114 (the top surface and the side surface of the semiconductor layer 113). A width of the channel region corresponds to the total of twice a height “a” and a width “b” of the semiconductor layer 113, while a gate length corresponds to a width L of the gate electrode 115.
As described above, FinFET is a field effect transistor where channel regions are formed at least in both sides of a protruding semiconductor layer, having a characteristic that it is generally excellent in prevention of short channel effect.